1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to an array substrate for an LCD and fabrication method thereof that has fewer masking processes.
2. Description of the Related Art
As modern society rapidly changes toward an information-oriented society, demand has increased for a flat panel display having superior characteristics advantages such as a slim profile, reduced weight, and low power consumption and high quality color reproduction. Liquid crystal displays (LCD), one of such flat panel displays, have been developed to meet these needs.
Generally, an LCD includes two substrates, each having an electrode formed on an inner surface. The two substrates are disposed to face each other, and a liquid crystal material is injected into a space between the two substrates. The LCD displays an image by applying a voltage to the electrode such that an electric field is generated within the liquid crystal material. The electric field manipulates the orientation of the liquid crystal molecules, which subsequently changes the transmission of light through the LCD.
The LCD can be fabricated in a variety of types. One of these is an active matrix LCD (AM-LCD) configuration in which thin film transistors (TFTs) and pixel electrodes connected to the TFTs are arranged in a matrix configuration, defining a plurality of liquid crystal cells. AM-LCDs are gaining in prominence due to superior resolution and reproduction capability of moving images.
In an AM-LCD, a lower array substrate has pixel electrodes formed on its surface, and an upper color substrate has a common electrode formed on its surface. As a voltage is applied to the electrodes of the array substrate and the color substrate, a vertical electric field is formed between the two substrates to manipulate the liquid crystal molecules. The AM-LCD has advantages such as superior transmittance and aperture ratio, and also prevents electrostatically-induced failure in the liquid crystal cells by having the upper common electrode serve as a ground.
The upper color substrate further includes a black matrix for preventing light leakage phenomenon at a portion other than the pixel electrodes.
The lower array substrate is formed by iterative processes of depositing thin films and patterning the deposited thin films by a photolithography using a mask. In the patterning of the deposited thin films, five or six masks are generally used. The number of masks used generally corresponds to the number of processes used for fabricating the array substrate.
A related art array substrate for an LCD and fabrication method thereof will now be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of an array substrate for an LCD according to the related art, and FIG. 2 is a sectional view taken along the line I-I′ of FIG. 1.
Referring to FIGS. 1 and 2, the array substrate for an LCD includes a transparent insulating substrate 110, a plurality of gate lines 121 formed on the transparent insulating substrate 110 in a horizontal direction, and a plurality of gate electrodes 122 extending from the plurality of gate lines 121. A gate insulator 130 is formed on the gate lines 121 and the gate electrodes 122, and an active layer 141 and an ohmic contact layer 151, 152 are sequentially formed on the gate insulator 130.
Further formed on the array substrate are a plurality of data lines 161 perpendicularly crossing the plurality of gate lines 121; a source electrode 162 extending from each of the date lines 161; a drain electrode 163 facing the source electrode 162 centering on the gate electrode 122; and a capacitor electrode 165 overlapping each of the plurality of gate lines 121.
The data lines 161, the source and drain electrodes 162 and 163, and the capacitor electrode 165 are covered with a passivation layer 170. The passivation layer 170 has first and second contact holes 171 and 172 exposing the drain electrode 163 and the capacitor electrode 165, respectively.
A pixel electrode 181 is formed at a pixel region on the passivation layer 170, the pixel region being defined by the crossed gate lines 121 and data lines 161. The pixel electrode 181 is electrically connected to the drain electrode 162 and the capacitor electrode 165 through the first and second contact holes 171 and 172, respectively.
The array substrate having the above construction can be fabricated by a photolithography process using five masks. Each photolithography process includes steps of rinsing the substrate, coating a photoresist film, developing and patterning the exposed photoresist film and etching a layer exposed by the photoresist pattern.
Accordingly, if a single photolithography process can be omitted, the overall fabrication time is reduced to a considerable degree and the total fabrication cost can be decreased. Also, since each photolithography process bears a certain risk of failure, eliminating a photolithography step may reduce the rate of substrate failures. Therefore, it is preferable that the number of the masks used be decreased during the fabrication of the array substrate.
In addition, since the array substrate has the passivation layer on an entire surface thereof including the TFTs, a costly plasma enhanced chemical vapor deposition (PECVD) equipment is generally required, which results in an increase in the fabrication cost.
Further, since the passivation layer has contact holes so as to connect the drain electrode and the capacitor electrode with the pixel electrode, a photolithography process for the formation of the contact holes is added, which may increase the fabrication cost and the risk of an open failure of the data lines.
A product failure may be caused due to a stepped portion of the contact holes during the formation of the pixel electrodes, and a picture quality may be reduced due to a point defect. Also, if the passivation layer is not uniformly formed, storage capacitance may be decreased, which may cause a spot failure on a screen.